With the semiconductor manufacturing technology entering the sub-65nm technology node, the crosstalk or the electromagnetic interactions caused by proximity effects of various circuit components cannot be neglected, which indirectly influences the RC time delay (resistance-capacitance time delay). The RC time delay in the metal interconnect process has become a main part of the RC time delays in the whole chip manufacturing process.
On the one hand, for reducing the RC time delay between the copper interconnect layers, the conventional SiO2 dielectric material (k≈4.2) is generally replaced by a dielectric material with a lower k (dielectric constant) value. For the technology nodes between 90 nm and 65 nm, the conventional dielectric material used in the industry is a SiOCH dielectric material with a dielectric constant between 2.6 and 3.0; For the 45 nm technology node and below, a porous SiOCH is used to further decrease the k value, whose dielectric constant value is between 2.0 and 2.5; an organic dielectric material containing C and H is also been used, whose dielectric constant value is between 2.2 and 2.6. Nowadays, the k value for the conventional ultra-low dielectric constant dielectric material has been reduced to about 2.0, however it still can't meet the requirement for further decreasing the metal line width.
On the other hand, thinner barrier layers and seed layers are generally used to increase the volume of copper in a dual damascene structure, so as to reduce the interconnect resistance to control the RC time delay. The magnetron sputtering physical vapor deposition (PVD) is a conventional method for depositing the barrier layers and the seed layers, however which have limitation of step coverage. Therefore, the current research is about using magnetron sputtering to form an ultra-thin tantalum nitride composite layer and an ultra-thin copper manganese seed layer, inserting an ultra-thin cobalt capping layer by chemical vapor deposition method, which further reduces the thickness of the barrier layer and the seed layer with ensuring the copper's gap-fill capability, and then a good result is received. Another exemplary research is about using atomic layer deposition (ALD) method to form the barrier/seed layer using ruthenium (Ru) and the alloy thereof, which receives a good copper gap filling capability and electrical property.
The conventional integration scheme of Cu/Low-k back-end-of-line is the Dual damascene process, including: depositing a intermetal dielectric material on the integrated circuit chip after the front-end-of-line process, positioning the vias and the trenches by the litho process, and then patterning the intermetal dielectric material to form a via pattern and a trench pattern by the dry-etching process; subsequently, removing the post-etch residues of the intermetal dielectric material; next, depositing the barrier layer and the seed layer, filling copper into the vias and trenches and then annealing the copper film; finally, planarizing the integrated circuit chip surface and to form a layer of the metal wiring process.
The thinning of the barrier layer and the seed layer is a general trend and the application of new materials and new deposition technologies are also inevitable. However, the via resistance is still one of the critical factors for the RC time delay in copper interconnects. The via etching process and cleaning process in the copper interconnect process could cause damages to surface of copper interconnects underlying the via; after the cleaning process, the surface of copper interconnects underlying the via exposes to the air, which will be oxidized; a barrier layer is deposited on the surface of copper interconnect underlying the via by a barrier layer deposition process; and the temperature for annealing the electroplated copper film is further decreased due to the introduction of ultra-low k dielectric materials. Those would increase the contact resistance between the copper in the via and the copper in the underlying interconnects, which will result an increase in RC time delay. Several methods have been used to decrease the contact resistance, such as: optimizing the etching process and the cleaning process, controlling queue time between the cleaning process and the depositing process, processing the surface with hydrogen gas before depositing the barrier layer, etching back the barrier layer on the bottom of the via during the barrier layer deposition, prolonging the processing time of annealing duration of the electroplated copper film.
Wherein, among the aforementioned factors which affect the contact resistance, the introduction of the porous low k dielectric material decreases the temperature for annealing the electroplated copper film to 180° C. and below. However, the copper film in the via processed under this temperature is difficult to fully release impurities, thus, the structure with large grain size is difficult to form; even if the anneal duration is extended, the growth of the copper grain in the via is still limited, thus the resistance of the cooper film in the via is relatively high, and the contact resistance of the via is difficult to decrease. Therefore, the conventional annealing process for the electroplated copper film limits the decrease of the contact resistance of the vias. It is necessary to put forward a new method for processing the electroplated copper film, so as to further decrease the contact resistance between the vias and the copper interconnects.